In certain circuit-oriented arrangements, what are known as pointer circuits are required. These circuits have a predetermined number of outputs. Only one output is selected to be in a determined logical state of two logically distinguishable states, while in contrast all other outputs are in the other logical state and are not selected.
By inputting a shift clock impulse, the one logical state can be displaced from the selected output to a next output adjacent to this output, so that the next output is subsequently in the one logical state and is selected, while all other outputs, including the one, are in the other logical state and are not selected. Pointer circuits of this sort can be used, for example, for the selection of a memory cell within a memory matrix (see European reference EP-A 0 738 974, Paul-Werner von Basse, Michael Bollu, Roland Thewes, Doris Schmitt-Landsiedel).
In previously known circuits of this sort, conventional shift register circuits are used, whereby the outputs of all registers except one contain the determined one logical state. Independent of the technology used, all these previously known circuits require a relatively high number of components per output. This relatively high space requirement can be very disadvantageous, particularly given application for the selection of a memory cell within a memory matrix, because the rows and column terminals in certain technologies or, respectively, in certain variant architectures of the cell field have very small spacings (see European reference EP-A 0 738 974, Paul-Werner von Basse, Michael Bollu, Roland Thewes, Doris Schmitt-Landsiedel; German reference P 44 37 581, L. Risch, F. Hofmann, W. Rosner, W. Krautschneider, "Verfahren zur Herstellung einer Festwertspeicherzellenanordnung mit vertikalen MOS-Transistoren,"; and European reference EP-A-0 78 84 866, W. Krautschneider, L. Risch, F. Hofmann, W. Rosner, "Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung").